In sample and hold circuits which employ sample data comparators, analog voltages are sampled and held on high impedance capacitive nodes using MOS switches. Since the gain of a single comparator is finite, many of these types of circuits use a plurality of serially connected comparators to increase the overall gain. FIG. 1 is a schematic drawing of such a sample and hold circuit 10 comprising three comparators 14, 18, and 22. An input voltage V.sub.IN to be sampled is provided to one terminal 23 of a capacitor C1. The other terminal 24 of capacitor C1 is coupled to a node E1 between an input terminal 26 of comparator 14 and a first terminal 32 of a feedback switch 30. The other input terminal of comparator 14 (not shown) is coupled to a reference potential. An output terminal 34 of comparator 14 is connected to a node 35 between a terminal 36 of a capacitor C2 and a second terminal 33 of feedback switch 30. Switch 30 also includes a control terminal 38 which receives a feedback switch control signal T1 for selectively allowing current to flow between first terminal 32 and second terminal 33.
The other terminal 39 of capacitor C2 is coupled to a node E2 between an input terminal 40 of comparator 18 and a first terminal 48 of a feedback switch 44. An output terminal 56 of comparator 18 is coupled to a node 57 between a terminal 62 of a capacitor C3 and a second terminal 52 of feedback switch 44. Feedback switch 44 also has a control terminal 60 which receives signal T1 for selectively allowing current to flow between first terminal 48 and second terminal 52 in the same manner as feedback switch 30. Output terminal 56 of comparator 18 is coupled to a terminal 62 of a capacitor C3. The other terminal 63 of capacitor C3 is coupled to a node E3 between an input terminal 64 of comparator 22 and a first terminal 72 of a feedback switch 68. An output terminal 78 of comparator 22 is coupled to a node 79 between a voltage output line 80 and a second terminal 74 of feedback switch 68. Feedback switch 68 also includes a control terminal 81 which receives signal T1 for selectively allowing current to flow between first terminal 72 and second terminal 74 in the same manner as feedback switches 30 and 44.
In this embodiment, current is allowed to flow through feedback switches 30, 44 and 68 for biasing comparators 14, 18 and 22 to their trip points when T1 is high. After V.sub.IN has been sampled, T1 goes low, feedback switches 30, 44 and 68 turn off, and comparators 14, 18 and 22 enter their high gain region of operation. At that time comparator 14 is capacitively coupled with C1 in order to independently store the DC bias point of comparator 14 while passing any AC signals. The same is true with comparator 18/capacitor C2 and comparator 22/capacitor C3. When feedback switches 30, 44 and 68 turn off, they inject charge into their corresponding high impedance storage nodes (i.e., nodes El, E2 and E3, respectively), and this alters the sampled voltage.
The altered voltage at node E1 contributes directly to the total offset error voltage for the circuit. For this circuit, the overall gain is the product of the gain of comparator 14, 18 and 22. Since the voltage at node E2 is isolated from the input by comparator 14, its contribution to the total offset error voltage is reduced by a factor equal to the gain of comparator 14. Similarly, the offset error voltage generated by switch 68 and appearing at node E3 is reduced by the product of the gain of comparators 14 and 18. Thus, the total offset error voltage V.sub.OEIN as sensed by the input to the series of comparators is EQU V.sub.OEIN =V.sub.OE1 +V.sub.OE2 /A1+V.sub.OE3 /(A1.times.A2).
Where V.sub.OE1, V.sub.OE2 and V.sub.OE3 are the offset error voltages at nodes E.sub.1, E.sub.2 and E.sub.3, respectively, and where A1, A2 and A3 are the gains for comparators 14, 18 and 22, respectively.
It should be apparent that, for single comparator gains greater than 1, the dominant contributor to V.sub.OEIN is V.sub.OE1. Thus, the effects of charge injection by feedback switch 30 should be minimized or eliminated wherever possible.
One known way to cancel the effect of the first stage error, V.sub.OE1, is to delay turning off feedback switch 44 until comparator 14 has settled to its charge-injection altered trip point. If feedback switch 44 is on while comparator 14 is settling, then the error generated by the first stage charge injection (V.sub.OE1) does not affect the output of the overall circuit. One technique for delaying or staggering the turnoff times of the individual feedback switches is to add several inverter delays between the control terminals of the feedback switches. Unfortunately, the amount of the delays is limited by the delay value of each inverter and the preset number of inverters that are built into the circuit. This makes it difficult if not impossible to compensate for charge injection if the operating environment of the circuit deviates from the assumptions made during the initial stages of the circuit design.